Wafer level testing refers to the process of subjecting semiconductor devices in wafer form to electrical testing. Such testing technology is useful not only for testing wafer level packaged devices but also for testing semiconductor devices sold as bare dies or known good dies (KGD) for conventional packaging. Wafer testing methods utilize test pads located in the scribe street regions, and the test pads are electrically connected to an external terminal through probe needles during wafer testing.